1. Field of the Invention
The present invention relates to a static memory cell with a pair of transfer MOS transistors, a pair of driver MOS transistors and a pair of load elements and, particularly, to a static memory cell constructed so as to enhance the operation speed and stability of a semiconductor device.
2. Description of the Related Art
Recently, the mounting density and the degree of integration of semiconductor devices are being more and more increased. Further, the operation of semiconductor devices is being more and more enhanced. Moreover, semiconductor elements such as MOS transistors etc. constituting semiconductor devices are miniaturized; at present, the practical design size thereof is set to about 0.25 .mu.m. For instance, in the case of static memory cells (hereinafter referred to briefly as SRAM) having a MOS structure, as the size of the memory cells is reduced, the operating voltage thereof is lowered, and the operating speed thereof is enhanced. In such a case, it is important not only to enhance the stability in operation of the semiconductor device including SRAM cells but also to lower the manufacturing costs thereof.
First, a SRAM cell will be described below. FIG. 1 is a circuit diagram showing an equivalent circuit of the SRAM cell. As shown in FIG. 1, the SRAM cell is ordinarily comprised of two high-resistance load elements and four N-channel MOS transistors. In this connection, it is added that MOS transistors are used, in stead of such load resistor elements, as the load elements in some cases. In the SRAM cell, the gate of a driver MOS transistor T.sub.1 and the drain of a driver MOS transistor T.sub.2 are connected to a storage node N.sub.2. The gate of the driver MOS transistor T.sub.2 and the drain of the driver MOS transistor T.sub.1 are connected to a storage node N.sub.1. Further, a load resistor element R.sub.1 is connected to the storage node N.sub.1, and a load resistor element R.sub.2 is connected to a storage node N.sub.2. A power supply voltage V.sub.cc is applied to the other ends of the load resistor elements R.sub.1 and R.sub.2. On the other hand, the source of the driver MOS transistor T.sub.1 and the source of the driver MOS transistor T.sub.2 are fixed to an earth potential V.sub.ss. Then, a flip-flop circuit is composed of the load resistor elements R.sub.1 and R.sub.2 and the driver MOS transistors T.sub.1 and T.sub.2.
Further, one of the source and drain of a transfer MOS transistor T.sub.3 is connected to the storage node N.sub.1, and one of the source and drain of a transfer MOS transistor T.sub.4 is connected to the storage node N.sub.2. A bit line BL.sub.1 is connected to the other of the source and drain of the transfer MOS transistor T.sub.3, and a bit line BL.sub.2 is connected to the other of the source and drain of the transfer MOS transistor T.sub.4. Moreover, a word line WL is connected to the ate of the transfer MOS transistor T.sub.3 and the gate of the transfer MOS transistor T.sub.4.
Further, one bit portion of storage information is stored in the SRAM cell thus constituted.
Heretofore, in a semiconductor device comprising SRAM cells as mentioned above, the MOS transistors, the load elements, the word line, the bit lines, etc. are disposed so as to be point-symmetrical, respectively, in order to secure the stability in the operation thereof.
FIG. 2 is a schematic drawing showing a typical conventional SRAM cell. In FIG. 2, the power supply wiring, the load resistor elements and the insulation films of the SRAM cell are not shown for the purpose of clarifying the cell pattern structure. Active element regions 102 and 102a are formed at the surface of a semiconductor substrate (not shown) of a silicon substrate or the like point-symmetrically with respect to a point of symmetry C. The active element regions 102 and 102a each have a bent shape and also have straight portions parallel to each other between the active element region 102 and the active element region 102a. Further, the active element regions 102 and 102a are surrounded by an isolating insulator film.
An inner connection portion 104a is formed in the bent portion of the active element region 102, and an inner connection portion 104 is formed in the bent portion of the active element region 102a. A gate electrode 103 of a driver MOS transistor is formed on the active element region 102 through a gate insulation film (not shown). The gate electrode 103 is connected to the active element region 102a through the inner connection portion 104. A gate electrode 103a of a driver MOS transistor is formed on the active element region 102a through a gate insulation film (not shown). The gate electrode 103a is connected to the active element region 102 through the inner connection portion 104a.
Further, a word line 105 is formed in such a manner as to be substantially perpendicular to the gate electrodes 103 and 103a and stride over the active element region 102. Further, a word line 105a is formed in such a manner as to be substantially perpendicular to the gate electrodes 103 and 103a and stride over the active element region 102a. The word lines 105 and 105a serve also as the gate electrodes of transfer MOS transistors.
Diffusion layers are formed in those portions of the active element regions 102 and 102a which are not covered by the gate electrode 103, the gate electrode 103a, the word line 105 or the word line 105a. The diffusion layers become the source and drain regions of n-channel MOS transistors. For instance, in FIG. 2, the portion of the active element region 102 which is located at the right side of the gate electrode 103 is used as the source region of the driver MOS transistor. Further, the portion of the active element region 102 which lies at the side lower than the word line 105 constitutes one of the source and drain of the transfer MOS transistor. Further, the portion of the active element region 102 which lies between the gate electrode 103 and the word line 105 is used as the drain region of the driver MOS transistor and the other of the source and drain of the transfer MOS transistor.
A ground wiring 106 is formed above the gate electrode 103 and the like. An inter-layer insulation film (not shown) having grounding contact holes 107 and 107a at predetermined positions is formed between the ground wiring 106 and the active element regions 102 and 102a, and electrically conductive layers (not shown) are buried in the grounding contact holes 107 and 107a. As a result, the ground wiring 106 is connected to predetermined regions of the diffusion layer in the active element region 102 and the diffusion layer in the active element region 102a.
Further, through not shown, a power supply wiring and a pair of load resistor elements are formed on the ground wiring 106 through the inter-layer insulation film. One end of each of the pair of load resistor elements is electrically connected to the gate electrodes 103 or 103a for the driver MOS transistor through the inner connection portion 104 or 104a. This region corresponds to the node N.sub.1 or N.sub.2 shown in FIG. 1.
Furthermore, bit line contact holes 108 and 108a are formed, respectively, on the portion of the active element region 102 or 102a constituting one of the source and drain of the transfer MOS transistor. Electrically conductive layers (not shown) are buried in the bit line contact holes 108 and 108a. Further, bit lines 109 and 109a are connected, respectively, to the electrically conductive layer in the bit line contact hole 108 or 108a.
In the conventional SRAM cell having the cell pattern structure thus constituted, the word lines 105 and 105a cross the bit lines 109 and 109a at right angles. Further, the gate electrodes 103 and 103a cross the word lines 105 and 105a at right angles. Furthermore, the channel direction of the driver MOS transistors and the channel direction of the transfer MOS transistors cross each other at right angles. That is, the direction in which the gate electrodes 103 and 103a extend is parallel to the direction in which the bit lines 109 and 109a extend. Thus, the size of the SRAM cell is constituted in such a manner that the SRAM cell is long in the direction in which the bit lines 109 and 109a extend and short in the direction in which the word lines 105 and 105a extend. Therefore, the parasitic capacitance between the bit lines is large. Further, the area over which the ground wiring 106 and the bit lines 109 and 109a overlap each other through the inter-layer insulation film is large, so that the parasitic capacitance between them is also large. Due to the fact that such large parasitic capacitances exist, the enhancement or increase in the operating speed of the semiconductor device on which conventional SRAM cells as mentioned above are mounted has its limit. Furthermore, two word lines are provided in the above-mentioned SRAM cell. This structure will hereinafter be referred to as the split word structure. Due to this structure, the dimensional miniaturization of the SRAM cell is insufficient.
Thus, there has been proposed a SRAM cell in which the pitch between the bit lines is enlarged to enhance the stabilization in low-voltage operation (Japanese Unexamined Patent Publication No. Hei 8-37241). FIG. 3 is a schematic drawing showing the SRAM cell disclosed in Japanese Unexamined Patent Publication No. Hei 8-37241. In FIG. 3, the power supply wiring, the ground wiring and the load resistor elements in the SRAM cell and the insulation films are not shown for the purpose of clarifying the cell pattern structure.
In the SRAM cell disclosed in the above-mentioned publication, active element regions 202 and 202a are formed symmetrically with respect to a point of symmetry D on a semiconductor substrate (not shown) of a silicon substrate or the like. Further, the active element regions 202 and 202a are surrounded by an element isolating insulation film. A gate electrode 203 of a driver MOS transistor is formed on the active element region 202 through a gate insulation film (not shown). The gate electrode 203 is connected to the active element region 202a through an inner connection portion (not shown). Further, a gate electrode 203a of a driver MOS transistor is formed on the active element region 202a through a gate insulation film (not shown). The gate electrode 203a is connected to the active element region 202 through an inner connection portion (not shown).
Further, a word line 204 is formed in a state extending in a direction inclined by 45.degree. with respect to the direction in which the gate electrodes 203 and 203a extend and striding over the active element region 202. Further, a word line 204a is formed in a state extending in a direction inclined by 45.degree. with respect to the direction in which the gate electrodes 203 and 203a extend and striding over the active element region 202a. The word lines 204 and 204a serve also as the gate electrodes of transfer MOS transistors.
Diffusion layers are formed in those portions of the active element regions 202 and 202a which are not covered by the gate electrode 203, the gate electrode 203a, the word line 205 or the word line 205a. The diffusion layers constitute the source and drain regions of the n-channel MOS transistors.
A ground wiring (not shown) is formed above the gate electrode 203 and the like. An inter-layer insulation film (not shown) provided with grounding contact holes 205 and 205a at predetermined positions thereof is formed between the ground wiring and the active element regions 202 and 202a, and electrically conductive layers (not shown) are buried in the grounding contact holes 207 and 207a. As a result, the ground wiring is connected to predetermined portions of the diffusion layer in the active element regions 202 and the diffusion layer in the active element region 202a.
Further, as in the case of the foregoing SRAM cell, a power supply wiring and a pair of load resistor elements are formed on the ground wiring through inter-layer insulation films.
Furthermore, bit line contact holes 206 and 206a are formed, respectively, on the portion of the active element region 202 or 202a constituting the source and drain regions of the transfer MOS transistor. Electrically conductive layers (not shown) are buried in the bit line contact holes 206 or 206a. The bit lines 207 and 207a are connected, respectively, to the electrically conductive layer in the bit line contact hole 206 or 206a.
In the conventional SRAM cell having the cell pattern constituted as mentioned above, the word lines 204 and 204a cross the bit lines 207 and 207a at right angles. The direction in which the gate electrodes 203 and 203a for the driver MOS transistors extend is inclined by about 45.degree. with reference to the direction in which the word lines 204 and 204a extend. Further, the channel direction of the driver MOS transistors and the channel direction of the transfer MOS transistors are directed in substantially the same direction. Thus, the dimension in the bit line direction of this SRAM cell can be shortened with reference to the foregoing conventional SRAM cell.
However, the area of the ground wiring and that of the bit lines which overlap each other through the inter-layer insulation film are still large; and thus, it is difficult to reduce the parasitic capacitance in the whole SRAM cell. Furthermore, the SRAM cell has the split word structure, so that the miniaturization of the SRAM cell is insufficient.